The present invention relates generally to computer graphics systems and more specifically to a method and apparatus for executing commands in a graphics controller chip.
Graphics controllers are designed to receive commands and display data from a host system, and generate display signals from display data and commands to display video images on a display system. FIG. 1 is a block diagram of a computer system 100 comprising such graphics controller 120, host 110, and display unit 130.
Graphics controller 120 may receive commands and display data from host 110 over system bus 112, and execute commands in the process of generating display signals on display bus 123 to display a video image of display data on display unit 130. Graphics controller 120 may generate more display data while executing commands received from host 110. Display data may comprise, for example, text data or graphics/video data in an RGB format.
Graphics controller 120 may store display data in display memory 140 before generating corresponding display signals on display bus 123. Each element of display data stored in display memory 140 may correspond to a pixel on the display unit. Such a data element is hereinafter referred to as pixel datum, and a plurality of such pixels are referred to as pixel data.
Commands received from host 110 may specify operations such as a move display block operation which may indicate to graphics controller 120 to move a block of display (hereinafter referred to as source display block) from one area of display memory 140 to another area (destination display block) on display memory 140. In some cases, source display block may be located in host 110, in which case host 110 may send display data of source display block also over system bus 112. In response, graphics controller 120 may move pixel data of source display block to memory locations corresponding to destination display block in display memory 140.
Host 110 may send several commands to graphics controller 120 to perform each operation. For example, to perform a move display block operation, host 110 may send a command to specify X-Y coordinates of starting location of source display block, another command to specify X-extent (i.e. length of display block in X-direction relative to starting address) and Y-extent of source display block, and yet another command to specify X-Y coordinates of starting address of destination display block. Host 110 may finally send another command to begin moving display data to memory locations corresponding to destination display block in display memory 140.
With the advent of graphics intensive applications (usually referred to as Graphical User Interface or GUI), computer system 100 may need to execute several graphics operations within a short duration. For example, click of a mouse by a computer user may require computer system 100 to execute several graphics operations. As each operation may require execution of several commands, host 110 may send a correspondingly large number of commands to graphics controller 120 over system bus 112.
One problem with prior art computer system 100 is that system bus 112 may not have bandwidth to support transfer of such a large number of commands and display data, and may therefore become a performance bottleneck in computer system 100. Such performance bottleneck may hinder performance throughput of computer system 100.
The performance bottleneck in system bus 112 may further be exacerbated as host 110 and graphics controller 120 may be operating at a higher speed and a larger bus width compared to system bus 112. For example, host 110 comprising a Pentium (TM) processor may be operating at 75 Mhz clock speed and a 64-bit internal bus, graphics controller 120 may be operating at 62.5 Mhz clock speed and a 64-bit internal bus, while system bus 112 comprising a PCI bus may be operating at 33 Mhz clock speed and 32-bit wide bus. Such a difference in clock rates and bus-widths in combination with graphics operations intensive GUI applications may cause a data throughput bottleneck on system bus 112, and hinder performance of computer system 100.
A graphics controller circuit includes a host interface which may receive a command from the host, and generate a plurality of instructions from the command. An execution circuit executes the plurality of instructions to execute, in effect, the command received from the host.
The graphics controller circuit may further include a register file comprising a plurality of registers. The host interface may generate a first set of instructions if the command accesses a first register in the register file, and a second set of instructions if the command accesses a second register. The first set of instructions may comprise accessing the first register. The second register in the present invention may be a virtual register, and the second set of instructions may include an instruction to access the first register.
By having such commands which are directed to virtual registers, and generating multiple instructions including a command to access a register in the register file, the graphics controller of the present invention may allow an access command to a register to be combined with other commands into one command on the system bus. Since several commands may be combined into one command on the system bus, the amount of data transferred on the system bus may be minimized.
The host interface of the present invention may comprise a command encoder for examining data on the bus, and for determining whether the command is addressed to the first register or the second register. The commander encoder may generate the first set of instructions if the command is addressed to the first register, and may generate the second set of instructions if the command is addressed to the second register.
The host interface may also include a FIFO queue for storing instructions generated by the command encoder, and for providing the instructions to the execution block. As the host interface generates multiple instructions from each command, the graphics controller instruction path and host supplied data-path may operate at a smaller bus-width saving silicon space. Graphics controller may execute such increased number of instructions as the graphics controller may be operating at higher speed than the system bus.
In the present invention, a plurality of commands to perform a move display block operation may include host supplied data. The host may send host data and the plurality of commands for the move display block operation over the host bus. The command encoder may store the host data and a set of instructions corresponding to the plurality of commands in the FIFO queue comprising a plurality of entries. The command encoder may also generate a tag bit indicative of whether data stored in each entry comprises a host datum or an instruction.
A FIFO output control circuit in the graphics controller circuit may examine the tag bit of each entry, and forward data in the entry to the execution block if the tag bit indicates that data in the corresponding entry comprises instructions or to the pixel processing block if the tag bit indicates that data in the corresponding entry comprises host data.